1. Field
Example embodiments described in this application relate to a semiconductor memory device, and in particular, to an internal voltage generator circuit for a semiconductor integrated circuit device.
2. Description of the Related Art
A general semiconductor memory device includes at least one memory cell array and each memory cell array includes a plurality of memory cells. A user can designate specific row and column addresses to thereby access memory cells. If row and column address are designated, corresponding memory cells are selected. In a read mode, data stored in the selected memory cells are output, and in a write mode, data are recorded in the selected memory cells. In the read mode, sense amplifiers are activated to sense the data in the selected memory cells and to output the sensed data as an output signal. This output signal may be transmitted to other circuits in the semiconductor memory device and finally to an external apparatus having requested the data. Examples of the external apparatus include a data processing system or a data operating system.
If a data read command is input to the semiconductor memory device, data in a memory cell corresponding to input addresses is input to input terminals of a sense amplifier through a bit line and a complementary bit line. When a first internal voltage is applied, the sense amplifier senses and amplifies a voltage difference between the input terminals and then outputs the data through I/O lines. Thereafter, when a second internal voltage is applied, the sense amplifier restores the sensed data in the memory cell through the bit line and the complementary bit line. However, in an early sensing operation, since a number of bit lines should be charged, a large amount of current is consumed. Therefore, a rapid drop in an internal array voltage VINTA may occur. Moreover, after charging the bit lines, the internal array voltage should be constantly maintained; however, it may be deviated from a reference voltage. Such a rapid drop in the internal array voltage and a difference between the internal array voltage and the reference voltage may degrade the performance of the semiconductor memory device.